Semiconductor devices are fabricated by creating a sequence of patterned and un-patterned layers where the features on patterned layers are spatially related to one another. Thus during fabrication, each patterned layer must be aligned with a previous patterned layer, and as such, the overlay between a first layer and a second layer must be taken into account. The overlay is the relative position between two or more layers of a semiconductor substrate such as, for example, a wafer. As semiconductor processes evolve to provide for smaller critical dimensions, and devices reduce in size and increase in complexity including number of layers, the alignment precision between layers becomes increasingly more important to the quality, reliability, and yield of the devices. The alignment precision is measured as overlay offset or overlay error, or the distance and direction a layer is offset from precise alignment with a previous layer. Misalignment of layers can cause performance issues and even potentially causing a device to fail due to, for example, a short caused by a misaligned interconnect layer.
Therefore, it is desired to accurately and efficiently measure the overlay offset between layers during processing to allow for possible correction. Current overlay metrology uses optically readable target marks or alignment marks printed onto layers of a semiconductor wafer during fabrication. The relative displacement of the marks is measured by irradiating the marks to measure the misregistration. As semiconductor devices decrease in dimensions this can become more challenging. Thus, what is desired are systems and methods that provide for accurate and efficient measurement of overlay error in semiconductor fabrication.